John A. Siemon, The Siemon Co.
Now that the Telecommunications Industry Association TR41.8.l working group on telecommunications cabling has successfully published standard TIA/EIA-568-A, numerous issues that have surfaced as a result of its ongoing efforts should be addressed. Last October, a special planning meeting was held to discuss these open issues and to formulate recommendations on a strategic plan to address them. During this meeting, each pending technical issue was assigned to one of three classifications. These classifications relate to their importance and the manner with which resulting specifications will be conveyed to the industry:
Critical technical issues
The following topics are pending investigation by members or task groups of TR41.8.1. Because of their critical technical nature, the approved technical resolutions for many of these issues will likely be released in the form of an addendum to TIA/EIA-568-A.
Short link resonance. Investigations of field transmission measurements on twisted-pair links has resulted in the discovery of a new phenomenon known as Oshort link resonance.O This resonance effect is characterized by peaks in near-end crosstalk performance at periodic intervals throughout the frequency range of testing. In links of short lengths, these peaks have been found to result in failure of the basic-link crosstalk requirements specified in TIA/EIA Technical Systems Bulletin 67, or TSB. The TR41.8.1 working group?s top priority is explaining and resolving this phenomenon.[Native Advertisement]
Hybrid-cable transmission requirements. Open office cabling and the need to support multiple telecommunications applications in a shared sheath have resulted in increased demand for hybrid cables. As a result, the hybrid-cable requirements that appear in both the 1991 and the 1995 editions of TIA/EIA-568 have come under increased scrutiny.
Unshielded twisted-pair cable and connecting hardware issues. Among the topics under investigation are test methods and requirements for balance and various harmonization issues with the International Standards Organization/International Electrotechnical Commission 11801 standard. Revision of the low-frequency limit for cable attenuation, clarification for temperature testing and restrictions on reversals/pair transpositions are also pending.
STP-A cable and connecting hardware issues. Among the topics under investigation are characteristic impedance, attenuation and near-end crosstalk temperature range for STP-A, or shielded twisted-pair, cables. Connector resistance and link performance requirements for the cabling type are also open.
Ongoing standards development
The following issues require development of new technical matter that will likely be released in the form of Interim Standards or TSBs. (Note that a TSB is an informative bulletin and not a standard.)
Y Technical specifications for 100-ohm patch cords. This draft TSB is being developed by the PN-2948 task group and will specify test methods and requirements for patch cord assemblies.
Y Technical specifications for 100-ohm STP cabling. This draft TSB is being developed by the PN-3193 task group. It will build on TIA/EIA-568-A by specifying additional technical requirements on shield effectiveness, installation practices and link performance relative to cabling with an overall shield.
Y Additional practices for open-office cabling. This draft TSB was developed by the PN-3398 task group. It specifies horizontal cabling methodologies in open-office environments by means of multiuser telecommunications outlets and consolidation points. Ballot is pending.
Y Additional cable requirements. Items under consideration are far-end crosstalk, balance and velocity of propagation. Specifications for testing channels and links that cover component characteristics, test methods, modeling, verification and link characteristics will also be addressed.
The third classification includes issues to be addressed in the third edition of the Commercial Building Telecommunications Cabling Standard, TIA/EIA-568-B, which will be covered in the TIA update next month.
John A. Siemon is vice president, engineering, at The Siemon Co. (Watertown, CT) and has been active in TIA?s engineering committee, TR-41.8, and its working groups since 1986. He is on the steering committee for the development of Revision B of TIA/EIA-568-A and also serves as the vice chair of the U.S. advisory group for international cabling standards.
Extended Display Identification Data (EDID) is a metadata format for display devices to describe their capabilities to a video source (e.g. graphics card or set-top box). The data format is defined by a standard published by the Video Electronics Standards Association (VESA).
EDID data structure includes manufacturer name and serial number, product type, phosphor or filter type, timings supported by the display, display size, luminance data and (for digital displays only) pixel mapping data.
DisplayID is a VESA standard targeted to replace EDID and E-EDID extensions with a uniform format suited for both PC monitor and consumer electronics devices.
EDID structure versions range from v1.0 to v1.4; all these define upwards-compatible 128-byte structures. EDID structure v2.0 defined a new 256-byte structure, but subsequently has been deprecated and replaced by v1.3 which support multiple exension blocks.HDMI versions 1.0–1.3c use EDID structure v1.3.
Before Display Data Channel (DDC) and EDID were defined, there was no standard way for a graphics card to know what kind of display device it was connected to. Some VGA connectors in personal computers provided a basic form of identification by connecting one, two or three pins to ground, but this coding was not standardized.
The channel for transmitting the EDID from the display to the graphics card is usually the I²C-bus, defined in DDC2B (DDC1 used a different serial format which never gained popularity).
The EDID is often stored in the monitor in a memory device called a serial PROM (programmable read-only memory) or EEPROM (electrically erasable PROM) and is accessible via the I²C-bus at address 0x50. The EDID PROM can often be read by the host PC even if the display itself is turned off.
Many software packages can read and display the EDID information, such as read-edid for Linux and DOS, PowerStrip for Microsoft Windows and XFree86 for Linux and BSD unix. Mac OS X natively reads EDID information and programs such as SwitchResX or DisplayConfigX can display the information as well as use it to define custom resolutions.
Enhanced EDID was introduced at the same time as E-DDC; it introduced EDID structure version 1.3 which supports multiple extensions blocks and deprecated EDID version 2.0 structure (although it can be supported as an extension). Data fields for preferred timing, range limits, and monitor name are required in E-EDID. E-EDID also supports dual GTF timings and aspect ratio change.[clarification needed]
With the use of extensions, E-EDID string can be lengthened up to 32 KBytes.
EDID Extensions assigned by VESA
- Timing Extension (00h)
- Additional Timing Data Block (CEA EDID Timing Extension) (02h)
- Video Timing Block Extension (VTB-EXT) (10h)
- EDID 2.0 Extension (20h)
- Display Information Extension (DI-EXT) (40h)
- Localized String Extension (LS-EXT) (50h)
- Microdisplay Interface Extension (MI-EXT) (60h)
- Display Transfer Characteristics Data Block (DTCDB) (A7h, AFh, BFh)
- Block Map (F0h)
- Display Device Data Block (DDDB) (FFh)
- Extension defined by monitor manufacturer (FFh): According to LS-EXT, actual contents varies from manufacturer. However, the value is later used by DDDB.
- August 1994, DDC standard version 1 – EDID v1.0 structure.
- April 1996, EDID standard version 2 – EDID v1.1 structure.
- 1997, EDID standard version 3 – EDID structures v1.2 and v2.0
- February 2000, E-EDID Standard Release A, v1.0 – EDID structure v1.3, EDID structure v2.0 deprecated
- September 2006 – E-EDID Standard Release A, v2.0 – EDID structure v1.4
Some graphics card drivers have historically coped poorly with the EDID, using only its standard timing descriptors rather than its Detailed Timing Descriptors (DTDs). Even in cases where the DTDs were read, the drivers are/were still often limited by the standard timing descriptor limitation that the horizontal/vertical resolutions must be evenly divisible by 8. This means that many graphics cards cannot express the native resolutions of the most common wide screenflat panel displays and liquid crystal display televisions. The number of vertical pixels is calculated from the horizontal resolution and the selected aspect ratio. To be fully expressible, the size of wide screen display must thus be a multiple of 16×9 pixels. For 1366×768 pixel Wide XGA panels the nearest resolution expressible in the EDID standard timing descriptor syntax is 1360×765 pixels, typically leading to 3 pixel thin black bars. Specifying 1368 pixels as the screen width would yield an unnatural screen height of 769.5 pixels.
Many Wide XGA panels do not advertise their native resolution in the standard timing descriptors, instead offering only a resolution of 1280×768. Some panels advertise a resolution only slightly smaller than the native, such as 1360×765. For these panels to be able to show a pixel perfect image, the EDID data must be ignored by the display driver or the driver must correctly interpret the DTD and be able to resolve resolutions whose size is not divisible by 8. Special programs are available to override the standard timing descriptors from EDID data. Even this is not always possible, as some vendors' graphics drivers (notably those of Intel) require specific registry hacks to implement custom resolutions, which can make it very difficult to use the screen's native resolution.
EDID 1.4 data format
|0–7||Fixed header pattern:|
|8–9||Manufacturer ID. This is a legacy Plug and Play ID assigned by Microsoft, which is a big-endian 16-bit value made up of three 5-bit letters: 00001=A, 00010=B, ... 11010=Z. E.g. 24 4d = 001001 0001001101 = "IBM".|
|Bit 15||(Reserved, always 0)|
|Bits 14–10||First letter of manufacturer ID (byte 8, bits 6–2)|
|Bits 9–5||Second letter of manufacturer ID (byte 8, bit 1 through byte 9 bit 5)|
|Bits 4–0||Third letter of manufacturer ID (byte 9 bits 4–0)|
|10–11||Manufacturer product code. 16-bit number, little-endian.|
|12–15||Serial number. 32 bits, little endian.|
|16||Week of manufacture, or model year flag. Week numbering is not consistent between manufacturers.|
|17||Year of manufacture, less 1990 (1990–2245). If week=255, it is the model year instead.|
|18||EDID version, usually 1 (for 1.3)|
|19||EDID revision, usually 3 (for 1.3)|
|20–24||Basic display parameters.|
|20||Video input parameters bitmap|
|Bit 7=1||Digital input. If set, the following bit definitions apply:|
|Bits 6–4||Bit depth: 000=undefined, 001=6, 010=8, 011=10, 100=12, 101=14, 110=16 bits per color, 111=reserved|
|Bits 3–0||Video interface: 0000=undefined, 0001=HDMIa, 0010=HDMIb, 0100=MDDI, 0101=DisplayPort|
|Bit 7=0||Analog input. If clear, the following bit definitions apply:|
|Bits 6–5||Video white and sync levels, relative to blank: 00=+0.7/−0.3 V; 01=+0.714/−0.286 V; 10=+1.0/−0.4 V; 11=+0.7/0 V|
|Bit 4||Blank-to-black setup (pedestal) expected|
|Bit 3||Separate sync supported|
|Bit 2||Composite sync (on HSync) supported|
|Bit 1||Sync on green supported|
|Bit 0||VSync pulse must be serrated when composite or sync-on-green is used.|
|21||Horizontal screen size, in centimetres (range 1-255). If vsize=0, landscape aspect ratio (range 1.00-3.54), datavalue = (AR×100)-99 (example: 16:9 = 79, 4:3 = 34)|
|22||Vertical screen size, in centimetres. If hsize=0, portrait aspect ratio (range 0.28-0.99), datavalue = (100/AR)-99 (example: 9:16 = 79, 3:4 = 34). If either byte is 0, screen size and aspect ration are undefined (e.g. projector)|
|23||Display gamma, factory default (range 1.00–3.54), datavalue = (gamma×100)-100 = (gamma−1)×100. If 225, gamma is defined by DI-EXT block.|
|24||Supported features bitmap|
|Bit 7||DPMS standby supported|
|Bit 6||DPMS suspend supported|
|Bit 5||DPMS active-off supported|
|Bits 4–3||Display type (digital): 00 = RGB 4:4:4; 01 = RGB 4:4:4 + YCrCb 4:4:4; 10 = RGB 4:4:4 + YCrCb 4:2:2; 11 = RGB 4:4:4 + YCrCb 4:4:4 + YCrCb 4:2:2|
|Bits 4–3||Display type (analog): 00 = Monochrome or Grayscale; 01 = RGB color; 10 = Non-RGB color; 11 = Undefined|
|Bit 2||Standard sRGB colour space. Bytes 25–34 must contain sRGB standard values.|
|Bit 1||Preferred timing mode specified in descriptor block 1. For EDID 1.3+ the preferred timing mode is always in the first Detailed Timing Descriptor. In that case, this bit specifies whether the preferred timing mode includes native pixel format and refresh rate.|
|Bit 0||Continuous timings with GTF or CVT|
10-bit CIE 1931 xy coordinates for red, green, blue, and white point
|25||Red and green least-significant bits (2−9, 2−10)|
|Bits 7–6||Red x value least-significant 2 bits|
|Bits 5–4||Red y value least-significant 2 bits|
|Bits 3–2||Green x value least-significant 2 bits|
|Bits 1–0||Green y value least-significant 2 bits|
|26||Blue and white least-significant 2 bits|
|27||Red x value most significant 8 bits (2−1,...,2−8). 0–255 encodes fractional 0–0.996 (255/256); 0–0.999 (1023/1024) with lsbits|
|28||Red y value most significant 8 bits|
|29–30||Green x and y value most significant 8 bits|
|31–32||Blue x and y value most significant 8 bits|
|33–34||Default white pointx and y value most significant 8 bits|
|35–37||Established timing bitmap. Supported bitmap for (formerly) very common timing modes.|
|35||Bit 7||720×400 @ 70 Hz (VGA)|
|Bit 6||720×400 @ 88 Hz (XGA)|
|Bit 5||640×480 @ 60 Hz (VGA)|
|Bit 4||640×480 @ 67 Hz (Apple Macintosh II)|
|Bit 3||640×480 @ 72 Hz|
|Bit 2||640×480 @ 75 Hz|
|Bit 1||800×600 @ 56 Hz|
|Bit 0||800×600 @ 60 Hz|
|36||Bit 7||800×600 @ 72 Hz|
|Bit 6||800×600 @ 75 Hz|
|Bit 5||832×624 @ 75 Hz (Apple Macintosh II)|
|Bit 4||1024×768 @ 87 Hz, interlaced (1024×768i)|
|Bit 3||1024×768 @ 60 Hz|
|Bit 2||1024×768 @ 72 Hz|
|Bit 1||1024×768 @ 75 Hz|
|Bit 0||1280×1024 @ 75 Hz|
|37||Bit 7||1152x870 @ 75 Hz (Apple Macintosh II)|
|Bits 6–0||Other manufacturer-specific display modes|
|38–53||Standard timing information. Up to 8 2-byte fields describing standard display modes.|
Unused fields are filled with
|Byte 0||X resolution, divided by 8, less 31 (256–2288 pixels, value 00 is reserved and should not be used)|
|Byte 1 bits 7–6||Image aspect ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9.|
(Versions prior to 1.3 defined 00 as 1:1.)
|Byte 1 bits 5–0||Vertical frequency, less 60 (60–123 Hz)|
|54–71||Descriptor 1||Descriptor blocks. Detailed timing descriptors, in decreasing preference order. After all detailed timing descriptors, additional descriptors are permitted: |
|126||Number of extensions to follow. 0 if no extensions.|
|127||Checksum. Sum of all 128 bytes should equal 0 (mod 256).|
|0–1||Pixel clock in 10 kHz units. (0.01–655.35 MHz, little-endian)|
|2||Horizontal active pixels 8 lsbits (0–4095)|
|3||Horizontal blanking pixels 8 lsbits (0–4095) End of active to start of next active.|
|4||Bits 7–4||Horizontal active pixels 4 msbits|
|Bits 3–0||Horizontal blanking pixels 4 msbits|
|5||Vertical active lines 8 lsbits (0–4095)|
|6||Vertical blanking lines 8 lsbits (0–4095)|
|7||Bits 7–4||Vertical active lines 4 msbits|
|Bits 3–0||Vertical blanking lines 4 msbits|
|8||Horizontal front porch (sync offset) pixels 8 lsbits (0–1023) From blanking start|
|9||Horizontal sync pulse width pixels 8 lsbits (0–1023)|
|10||Bits 7–4||Vertical front porch (sync offset) lines 4 lsbits (0–63)|
|Bits 3–0||Vertical sync pulse width lines 4 lsbits (0–63)|
|11||Bits 7–6||Horizontal front porch (sync offset) pixels 2 msbits|
|Bits 5–4||Horizontal sync pulse width pixels 2 msbits|
|Bits 3–2||Vertical front porch (sync offset) lines 2 msbits|
|Bits 1–0||Vertical sync pulse width lines 2 msbits|
|12||Horizontal image size, mm, 8 lsbits (0–4095 mm, 161 in)|
|13||Vertical image size, mm, 8 lsbits (0–4095 mm, 161 in)|
|14||Bits 7–4||Horizontal image size, mm, 4 msbits|
|Bits 3–0||Vertical image size, mm, 4 msbits|
|15||Horizontal border pixels (one side; total is twice this)|
|16||Vertical border lines (one side; total is twice this)|
|Bits 6–5||Stereo mode: 00=No stereo; other values depend on bit 0:|
Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar, sync=1 during left; 11=4-way interleaved stereo
Bit 0=1: 01=Right image on even lines; 10=Left image on even lines; 11=side-by-side
|Bit 4=0||Analog sync.|
If set, the following bit definitions apply:
|Bit 3||Sync type: 0=Analog composite; 1=Bipolar analog composite|
|Bit 2||VSync serration (HSync during VSync)|
|Bit 1||Sync on all 3 RGB lines (else green only)|
|Bits 4-3=10||Digital composite (on HSync).|
If set, the following bit definitions apply:
|Bit 2||Vertical sync polarity (0=negative, 1=positive)|
|Bits 4-3=11||Digital separate sync.|
If set, the following bit definitions apply:
|Bit 2||VSync serration (HSync during VSync)|
|Bit 1||Horizontal Sync polarity (0=negative, 1=positive)|
|Bit 0||2-way line-interleaved or side-by-side interleaved stereo, if bits 6–5 are not 00.|
When used for another descriptor, the pixel clock and some other bytes are set to 0:
|0–1||Zero, indicates not a detailed timing descriptor|
|3||Descriptor type. – currently defined. – reserved for vendors.|
|5–17||Defined by descriptor type. If text, code page 437 text, terminated (if less than 13 bytes) with LF and padded with SP.|
Currently defined descriptor types are:
- 0xFF: Display serial number (ASCII text)
- 0xFE: Unspecified text (ASCII text)
- 0xFD: Display range limits. 6- or 13-byte (with additional timing) binary descriptor.
- 0xFC: Display name (ASCII text).
- 0xFB: Additional white point data. 2× 5-byte descriptors, padded with .
- 0xFA: Additional standard timing identifiers. 6× 2-byte descriptors, padded with .
- 0xF9 Display Color Management (DCM).
- 0xF8 CVT 3-Byte Timing Codes.
- 0xF7 Additional standard timing 3.
- 0x10 Dummy identifier.
- 00-0x0Fh Manufacturer reserved descriptors.
|0–3||Standard header, byte 3 = 0xFD.|
|4||Offsets for display range limits|
|Bits 7–4||Unused, must be 0.|
|Bits 3–2||Horizontal rate offsets: 00=None, 10=+255 kHz for Max rate, 11=+255 kHz for Max and Min rates|
|Bits 1–0||Vertical rate offsets: 00=None, 10=+255 Hz for Max rate, 11=+255 Hz for Max and Min rates|
|5||Minimum vertical field rate (1–255 Hz) (256–512 Hz if offset)|
|6||Maximum vertical field rate (1–255 Hz) (256–512 Hz if offset)|
|7||Minimum horizontal line rate (1–255 kHz) (256–512 kHz if offset)|
|8||Maximum horizontal line rate (1–255 kHz) (256–512 kHz if offset)|
|9||Maximum pixel clock rate, rounded up to 10 MHz multiple (10–2550 MHz)|
|10||Extended timing information type:|
: Default GTF (when Basic display parameters byte 24 bit 0 is set.
|11-17||Video timing parameters (if byte 10 is or , padded with ).|
|11||Reserved, must be 0.|
|12||Start frequency for secondary curve, divided by 2 kHz (0–510 kHz)|
|13||GTF C value, multiplied by 2 (0–127.5)|
|14–15||GTF M value (0–65535, little-endian)|
|16||GTF K value (0–255)|
|17||GTF J value, multiplied by 2 (0–127.5)|
|11||Bits 7–4||CVT major version (1-15)|
|Bits 3–0||CVT minor version (0-15)|
|12||Bits 7–2||Additional clock precision in 0.25 MHz increments|
(to be subtracted from byte 9 Maximum pixel clock rate)
|Bits 1–0||Maximum active pixels per line, 2-bit msb|
|13||Maximum active pixels per line, 8-bit lsb (no limit if 0)|
|14||Aspect ratio bitmap|
|Bits 2–0||Reserved, must be 0.|
|15||Bits 7–5||Aspect ratio preference: 000=4:3, 001=16:9, 010=16:10, 011=5:4, 100=15:9|
|Bit 4||CVT-RB reduced blanking (preferred)|
|Bit 3||CVT standard blanking|
|Bits 2–0||Reserved, must be 0.|
|16||Scaling support bitmap|
|Bit 7||Horizontal shrink|
|Bit 6||Horizontal stretch|
|Bit 5||Vertical shrink|
|Bit 4||Vertical stretch|
|Bits 3–0||Reserved, must be 0.|
|17||Preferred vertical refresh rate (1–255)|
|0–4||Standard header, byte 3 = 0xFB.|
|5||White point index number (1–255) Usually 1; 0 indicates descriptor not used.|
|6||White point CIE xy coordinates least-significant bits (like EDID byte 26)|
|Bits 7–4||Unused, must be 0.|
|Bits 3–2||White point x value least-significant 2 bits|
|Bits 1–0||White point y value least-significant 2 bits|
|7||White point x value most significant 8 bits (like EDID byte 27)|
|8||White point y value most significant 8 bits (like EDID byte 28)|
|9||datavalue = (gamma−1)×100 (1.0–3.54, like EDID byte 23)|
|10–14||Second descriptor, like above. Index number usually 2.|
|15–17||Unused, padded with .|
|0–4||Standard header, byte 3 = 0xF9.|
|6||Red a3 lsb|
|7||Red a3 msb|
|8||Red a2 lsb|
|9||Red a2 msb|
|10||Green a3 lsb|
|11||Green a3 msb|
|12||Green a2 lsb|
|13||Green a2 msb|
|14||Blue a3 lsb|
|15||Blue a3 msb|
|16||Blue a2 lsb|
|17||Blue a2 msb|
|0–4||Standard header, byte 3 = 0xF8.|
|6-8||CVT timing descriptor #1|
|6||Addressable lines 8-bit lsb|
|7||Bits 7–4||Addressable lines 4-bit msb|
|Bits 3–2||Preferred vertical rate: 00=50 Hz, 01=60 Hz, 10=75 Hz, 11=85 Hz|
|Bits 1–0||Unused, must be 0.|
|8||Bit 7||Unused, must be 0.|
|Bits 6–5||Aspect ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9|
|Vertical rate bitmap|
|Bit 4||50 Hz CVT|
|Bit 3||60 Hz CVT|
|Bit 2||75 Hz CVT|
|Bit 1||85 Hz CVT|
|Bit 0||60 Hz CVT reduced blanking|
|9-11||CVT timing descriptor #2|
|12-14||CVT timing descriptor #3|
|15-17||CVT timing descriptor #4|
|0–4||Standard header, byte 3 = 0xF7.|
|6||Bit 7||640×350 @ 85 Hz|
|Bit 6||640×400 @ 85 Hz|
|Bit 5||720×400 @ 85 Hz|
|Bit 4||640×480 @ 85 Hz|
|Bit 3||848×480 @ 60 Hz|
|Bit 2||800×600 @ 85 Hz|
|Bit 1||1024×768 @ 85 Hz,|
|Bit 0||1152×864 @ 85 Hz|
|7||Bit 7||1280×768 @ 60 Hz (CVT-RB)|
|Bit 6||1280×768 @ 60 Hz|
|Bit 5||1280×768 @ 75 Hz|
|Bit 4||1280×768 @ 85 Hz|
|Bit 3||1280×960 @ 60 Hz|
|Bit 2||1280×960 @ 85 Hz|
|Bit 1||1280×1024 @ 60 Hz|
|Bit 0||1280×1024 @ 85 Hz|
|8||Bit 7||1360×768 @ 60 Hz (CVT-RB)|
|Bit 6||1280×768 @ 60 Hz|
|Bit 5||1440×900 @ 60 Hz (CVT-RB)|
|Bit 4||1440×900 @ 75 Hz|
|Bit 3||1440×900 @ 85 Hz|
|Bit 2||1440×1050 @ 60 Hz (CVT-RB)|
|Bit 1||1440×1050 @ 60 Hz|
|Bit 0||1440×1050 @ 75 Hz|
|9||Bit 7||1440×1050 @ 85 Hz|
|Bit 6||1680×1050 @ 60 Hz (CVT-RB)|
|Bit 5||1680×1050 @ 60 Hz|
|Bit 4||1680×1050 @ 75 Hz|
|Bit 3||1680×1050 @ 85 Hz|
|Bit 2||1600×1200 @ 60 Hz|
|Bit 1||1600×1200 @ 65 Hz|
|Bit 0||1600×1200 @ 70 Hz|
|10||Bit 7||1600×1200 @ 75 Hz|
|Bit 6||1600×1200 @ 85 Hz|
|Bit 5||1792×1344 @ 60 Hz|
|Bit 4||1792×1344 @ 75 Hz|
|Bit 3||1856×1392 @ 60 Hz|
|Bit 2||1856×1392 @ 75 Hz|
|Bit 1||1920×1200 @ 60 Hz (CVT-RB)|
|Bit 0||1920×1200 @ 60 Hz|
|11||Bit 7||1920×1200 @ 75 Hz|
|Bit 6||1920×1200 @ 75 Hz|
|Bit 5||1920×1440 @ 60 Hz|
|Bit 5||1920×1440 @ 75 Hz|
|Bits 3–0||Unused, must be 0.|
|12-17||Unused, must be 0.|
EIA/CEA-861 extension block
The CEA EDID Timing Extension was first introduced in EIA/CEA-861, and has since been updated several times, most notably with the −861B revision (which was version 3 of the extension, adding Short Video Descriptors and advanced audio capability/configuration information), −861D (published in July 2006 and containing updates to the audio segments), −861E, and −861F which was published on June 4, 2013. According to Brian Markwalter, senior vice president, research and standards, CEA, −861F "includes a number of noteworthy enhancements, including support for several new Ultra HD and widescreen video formats and additional colorimetry schemes.”
The most recent version, CTA-861-G, originally published in November 2016, was made available for free in November 2017 after some necessary changes due to a trademark complaint.
Version 1 (as defined in −861) allowed the specification of video timings only through the use of 18-byte Detailed Timing Descriptors (DTD) (as detailed in EDID 1.3 data format above). In all cases, the "preferred" timing should be the first DTD listed in a CEA EDID Timing Extension.
Version 2 (as defined in −861A) added the capability to designate a number of DTDs as "native" and also included some "basic discovery" functionality for whether the display device contains support for "basic audio", YCbCr pixel formats, and underscan.
Version 3 (from the −861B spec) allows two different ways to specify the timings of available digital TV[clarification needed] formats: As in Version 1 & 2 by the use of 18-byte DTDs, or by the use of the Short Video Descriptor (SVD) (see below). HDMI 1.0 -1.3c uses this[which?] version.
Version 3 also includes four new optional types of data blocks: Video Data Blocks containing the aforementioned Short Video Descripter (SVD), Audio Data Blocks containing Short Audio Descriptors (SAD), Speaker Allocation Data Blocks containing information about the speaker configuration of the display device, and Vendor Specific Data Blocks which can contain information specific to a given vendor's use.